Method of converting a stream of databits of a binary information signal into a stream of databits of a constrained binary channel signal, device for encoding, signal comprising a stream of databits of a constrained binary channel signal, record carrier and device for decoding

ABSTRACT

The invention relates to a method of converting a stream of databits of a binary information signal into a stream of databits of a constrained binary channel signal. This stream of databits of the binary information signal is divided into n-bit information words. These information words are converted into m 1 -bit channel words, in accordance with a channel code C 1 , or m 2 -bit channel words, in accordance with a channel code C 2 , where m 1 , m 2  and n are integers for which it holds that m 2 &gt;m 1 ≧n. The m 2 -bit channel word is chosen from of at least two m 2 -bit channel words, at least two of which have opposite parities, the concatenated m 1 -bit channel words and the m 2 -bit channel words complying with a runlength constraint of the binary channel signal. The method comprises the repetitive and/or alternate steps of:  
     selecting the m 1 -bit channel word from a set out of a plurality of sets of m 1 -bit channel words, each set comprising only m 1 -bit channel words having a beginning part out of a subset of beginning parts of the m 1 -bit channel words, each set being associated with a coding state of channel code C 1 , the coding state being established in dependence upon an end part of the preceding channel word, or:  
     selecting the m 2 -bit channel word from a set out of a plurality of sets of m 2 -bit channel words, which selection depends on the end part of the preceding channel word, each set comprising only m 2 -bit channel words having a beginning part out of a subset of beginning parts of the m 2 -bit channel words belonging to said set, each set being associated with a coding state of channel code C 2 , the coding state being established in dependence upon an end part of the preceding channel word.  
     The end parts of the m 1 -bit channel words in a coding state of channel code C 1  and the beginning parts of the m 2 -bit channel words in a set of channel code C 2  are arranged to comply with said runlength constraint.  
     The invention further relates to a device for encoding, a signal comprising a stream of databits of a constrained binary channel signal, a record carrier and a device for decoding.

[0001] The invention relates to a method of converting a stream ofdatabits of a binary information signal into a stream of databits of aconstrained binary channel signal, wherein the stream of databits of thebinary information signal is divided into n-bit information words, saidinformation words being converted into m₁-bit channel words inaccordance with a channel code C₁, or m₂-bit channel words, inaccordance with a channel code C₂, where m₁, m₂ and n are integers forwhich it holds that m₂>m₁≧n, wherein the m₂-bit channel word is chosenfrom at least two m₂-bit channel words, at least two of which haveopposite parities, the concatenated m₁-bit channel words and the m₂-bitchannel words complying with a runlength constraint of the binarychannel signal.

[0002] The invention also relates to a device for encoding a stream ofdatabits of a binary information signal into a stream of databits of aconstrained binary channel signal. The invention also relates to asignal comprising a stream of databits of a constrained binary channelsignal. The invention further relates to a record carrier and to adevice for decoding the constrained binary channel signal.

[0003] The invention is in the field of channel coding, in particular inrunlength limited channel coding. The length of time, expressed inchannel bits, between consecutive signal transitions is usually calledthe runlength. Different constraints can be imposed on a channel code,e.g. resulting in a runlength limited channel code. In such a code, asequence of channel words is characterized by two parameters, ad-constraint and a k-constraint. In (d,k) domain a logical “one”indicates a transition in the signal waveform. A (d,k) sequencesatisfies the following two conditions: due to the d-constraint, twologic “ones” are separated by a run of at least d consecutive “zeroes”;due to the k-constraint two logic “ones” are separated by a run of atmost k consecutive “zeroes”. The (d,k) sequence is converted from the(d,k) domain into a runlength-limited (RLL) sequence of the type (d,k)in the RLL domain upon precoding in a IT precoder. This RLL sequencecomprises elements with runlengths (either an array of consecutivezeroes or an array of consecutive ones) of d+1 at minimum and k+1 atmaximum between subsequent signal reversals in the information signal.The values of (d+1) and (k+1) indicate the minimum and maximumrunlengths of the element allowed in the sequence. It is noted that theterm element can be used to indicate both an element of a (d,k) sequenceor an element of an RLL sequence. An element is considered to beextending over a runlength in the RLL domain or (d,k) domain.

[0004] In runlength limited channel coding, each information word isconverted into a channel word according to predefined rules ofconversion, these channel words forming a modulated signal.

[0005]Research Disclosure, January 1992, page 32, 33340, discloses acoding method according to which n-bit information words are alternatelyconverted into m₁-bit channel words and m₂-bit channel words, where n,m₁ and m₂ are integers and n<m₁≦m₂. For each n-bit information word,there are two m₂-bit channel words available having mutually differentdisparities. A channel word is selected so that the current runningdigital sum in the channel signal shows a behaviour in accordance with adesired pattern as a function of time, for example a DC-free coding inthe channel signal.

[0006] In other words, there are two channel codes involved in theResearch Disclosure, one with an n-to-m₁ mapping of information wordsinto channel words, which can be referred to as the main code C₁, andthe other with an n-to-m₂ mapping, with two m₂-bit channel words, whichcan be referred to as the dual code C₂.

[0007] The efficiency of a channel code can be expressed by using the(information) rate of the channel code. This rate R of a channel code isdefined as the quotient n/m, in which the code translated n binary user(or information) symbols into m binary channel symbols. As explainedabove, in runlength limited channel coding, the channel words mustcomply with certain constraints, for example a d-constraint and ak-constraint. Due to these restrictions, the number of bit combinationswhich may represent the information words is lowered and therefore therate will decrease.

[0008] It is an object of the invention to realize an efficient methodof encoding a stream of information words into a constrained stream ofchannel words.

[0009] The method in accordance with the invention is characterized inthat the method comprises the repetitive and/or alternate steps of:

[0010] selecting the m₁-bit channel word from a set out of a pluralityof sets of m₁-bit channel words, each set comprising only m₁-bit channelwords having a beginning part out of a subset of beginning parts of them₁-bit channel words, each set being associated with a coding state ofchannel code C₁, the coding state being established in dependence uponan end part of the preceding channel word, or:

[0011] selecting the m₂-bit channel word from a set out of a pluralityof sets of m₂-bit channel words, each set comprising only m₂-bit channelwords having a beginning part out of a subset of beginning parts of them₂-bit channel words belonging to said set, each set being associatedwith a coding state of channel code C₂, the coding state beingestablished in dependence upon an end part of the preceding channelword,

[0012] the end parts of the m₁-bit channel words in a coding state ofchannel code C₁ and the beginning parts of the m₂-bit channel words in aset of channel code C₂ being arranged to comply with said runlengthconstraint.

[0013] By repetitively or alternately performing said steps and byarranging the end parts of the m₁-bit channel words in a coding state ofchannel code C₁ and the beginning parts of the m₂-bit channel words in acoding state of channel code C₂, the beginning parts of the m₂-bitchannel words can be applied to the coding states of channel code C₁,thereby realizing the constrained binary channel signal; and vice versawhen arranging the end parts of the m₂-bit channel words and thebeginning parts of the m₁-bit channel words.

[0014] The invention is based on the recognition that the coding statesof two different channel codes can be combined by arranging thebeginning parts and the end parts of the channel words of the channelcodes, so that end parts in the channel code C₁ match with beginningparts of the sets of m₁-bit channel words, but also with the beginningparts of the sets of m2-bit channel words. A multiple-state descriptionof encoder and decoder yields channel codes with high efficiency orinformation rate.

[0015] Another method according to the invention is characterized inthat the number of coding states of channel code C₁ is equal to thenumber of coding states of channel code C₂.

[0016] In the case where for the dual code C₂, two m₂-bit channel wordswith opposite parity can be used for each n-bit information word, it ispossible to use these channel words for influencing predeterminedproperties of the binary channel signal. In order to be able to complywith the constraints of the constrained stream of channel words, it isadvantageous that the end parts of the m₁-bit channel words in a codingstate of channel code C₁ and the beginning parts of the m₂-bit channelwords in a coding state of channel code C₂ are arranged that the numberof coding states of channel code C₁ is equal to the number of codingstates of channel code C₂. In this way, the coding tables can belimited. Parts of the -coding states of channel code C₁ can for examplebe similar or equal to parts of the coding states of channel code C₂.This results in an easier implementation of coding and decoding inhardware and/or software.

[0017] The channel codes according to the invention may be uniquelydescribed in terms of a so-called finite-state-machine (FSM).Transitions between the states of the FSM correspond to the emission ofchannel words in accordance with n-bit information words that enter theencoder. This implies that—in order to have a valid code—from each stateof the FSM, there must be leaving at least 2^(n) transitions towards allstates of the FSM. With the FSM being in a given state, a given n-bitinformation word does not only determine the m-bit channel words, butalso the next-state from which the next n-bit information word enteringthe encoder, is to be encoded.

[0018] Another method according to the invention is characterized inthat the end part of any m₁-bit channel word has a multiplicity y₁, themultiplicity y₁ being the number of different states of the channel codeC₁ said end part may establish, and that the end part of any m₂-bitchannel word has a multiplicity y₂, the multiplicity y₂ being the numberof states of the channel code C₂ said end may establish and in thaty₁=y₂ if the end part of the m₁-bit channel word is equal to the endpart of the m₂-bit channel word.

[0019] Each end part of the m₁-bit channel word has a multiplicity y₁,the multiplicity y₁ being the number of states of the channel code C₁said end part is permitted in, and each end part of the m₂-bit channelword has a multiplicity y₂, the multiplicity y₂ being the number ofstates of the channel code C₂ said end part is permitted in. It is notnecessary that the multiplicity of an end part of a word is used for100%. It is advantageous that y₁=y₂, if the end part of the m₁-bitchannel word is equal to the end part of the m₂-bit channel word. Inthis way the coding states of channel code C₁ and the coding states ofchannel code C₂ can be alternated in order that the constrained binarychannel signal, comprising the concatenated m₁-bit channel words and them₂-bit channel words, obeys a constraint of the binary channel signal.Using an equal multiplicity results in an easier implementation ofcoding and decoding in hardware and/or software.

[0020] Another method according to the invention is characterized inthat said at least two m₂-bit channel words establish the same state.

[0021] We have so far defined the dual code C₂ as having the followingproperties: it is a code with n-to-m₂ mapping, where each n-bitinformation word can be represented by at least two channel words, amongwhich at least two have opposite parities. The latter property isintended for influencing some envisaged properties of the encodedchannel bitstream, e.g. control of the DC-content of the code.

[0022] However, the guaranteed parity selection property of the dualcode C₂ is not satisfactory to guarantee, for instance a DC-control of apredetermined performance level. This is due to the fact that, in theFSM, both channel words of the dual code C₂ may lead to differentnext-states: this would imply that the subsequent encoding paths for thetwo distinct choices of the channel words of C₂ may be completelydifferent, and that the overall parity of the bitstream between the twochannel words encoded with the dual code, can be different, so that theDC-control which is driven by the decisions of the words of the dualcode C₂, gets frustrated, leading to a potentially poor performance withrespect to the desired property of the channel bitstream.

[0023] It is therefore advantageous to design the states of the FSMs ofthe channel codes C₁ and C₂ in order that, upon converting an n-bitinformation word into the two m₂-bit channel words, the two m₂-bitchannel words not only leave from the same state in the FSM but also endin the same next-state in the FSM. In other words, both channel words ofC₂, corresponding to the same n-bit information word, have the samenext-state. The use of this so-called “same-nextstate” property of thedual code C₂ leads to the following advantage: the above frustration ofthe control via C₂ is eliminated: the encoding paths of the main code C₁between successive points where C₂ is used in the stream of informationwords is now completely fixed, thus implying the same parity of thechannel bitstream encoded with C₁ between successive locations where C₂is used, independent of the coding choices of C₂.

[0024] Having a choice between the two m₂-bit channel words, enablesperforming DC-control in order to achieve a so-called DC-balanced or aDC-free code. E.g. in optical recording, DC-balanced codes are employedto circumvent or reduce interaction between the data written on a recordcarrier and the servosystems that follow a track on the record carrier.The bytes encoded with the dual code C₂ are the points in the channelbitstream that allow for control of the DC-content. Apart fromcontrolling the DC-content of the channel bitstream the bytes encodedwith the dual code C₂ can be used for influencing other properties ofthe channel bitstream.

[0025] Straightforward DC-control procedures make a decision at eachDC-control point depending on an RDS-related criterion, which isevaluated only for the channel bitstream ranging from the consideredDC-control point up to the next one. Such locally optimal decisionstrategy does not exploit all DC-control potential of the channel code.A better approach is to apply look-ahead DC-control, i.e. to build adecision tree of depth N in which the decision at a given DC-controlpoint is determined also by its impact on the subsequent channelbitstream in combination with the future decisions at the next N-IDC-control points. Each path through the decision tree consists of Nbranches, and the RDS-criterion applies for the complete path. N-foldLook-Ahead DC-control implies 2^(N) encoding paths, with the drawback ofa higher encoder complexity since each byte needs to be encoded 2 times.

[0026] For the channel code according to this embodiment, the pathfollowed through the FSM during encoding does not depend on the actualpath followed through the N-fold decision tree. This is due to the“same-next-state” property of the two coding options at the dual codeC₂. Hence, all bytes related to the main code C₁, need to be encodedonly once, whereas all bytes related to the dual code C₂, need to beencoded just twice. This reduces the hardware complexity of the encodingtree down to that related to a simple sequential encoding withoutfurther branching. Only the N-fold decision tree of RDS-criteria alongthe 2^(N) paths remains, resulting in a lower complexity.

[0027] An RDS-related criterion can be, for example, the maximumabsolute value of the RDS-value itself (first order spectral zero), butalso the integrated RDS-value in time (second order spectral zero) or acombination of both can be used. Also the sum variance (SV) can be usedas a criterion.

[0028] Another method according to the invention is characterized inthat the sets of channel words of channel code C₁ and the coding statesof channel code C₂ are arranged that binary channel signal formed by theconcatenated m₁-bit channel words and the m₂-bit channel words complywith a Repeated-Minimum-Runlength-Limitation=6 constraint on the binarychannel.

[0029] Constraints can also limit the number of consecutive runlengthsof the same length. For example, when imposing an RMTR (Repeated MinimumTransition Runlength) constraint of n on a d=2 channel code, thisconstraint implies that the number of successive 3T runlengths in thesequence of channel words is limited to n. In order to realize aRepeated-Minimum-Runlength-Limitation of 6 constraint, code tables aredesigned from which possible channel words that could lead to theviolation of the RMTR-constraint are eliminated (e.g. the word (100)⁵).In another way, the RMTR-constraint can also be obeyed by substitutingchannel words or patterns when an RMTR-violation would take place. Moreinformation about this RMTR (Repeated Minimum Transition Runlength)constraint can be found in published patent application WO99/63671-A1(PHQ 98.023).

[0030] Another method according to the invention is characterized inthat the ratio between the number of m₁-bit channel words and the numberof m₂-bit channel words is determined in dependence of a chosen measureof DC-control.

[0031] It should be noted that the two channel codes C₁ and C₂ areindependent codes each, which can also be used separately. C₁ istypically a high-rate code with no systematic structure to steer certainextra properties of the encoded channel bitstream on top of theenvisaged runlength constraints (d, k, RMTR). C₂ is a slightlylower-rate code and the rateloss as compared to C₁, is used for asystematic structure aimed at steering the additionally requiredproperties. For the invention as described in detail below, C₁ and C₂are to be used in combination, from which the term combi-code isderived, but it should be realized that any combination pattern ispossible. The more the main code C₁ is used (relative to the use of thedual code C₂), the higher the rate will be of the overall combinationcode, but also the lower the controlling capacity will be for the extraenvisaged properties of the channel bitstream. With respect to thelatter, a maximum of control can be achieved by using the dual code C₂all the time, and a minimum of control is the case when using only themain code C₁. It can therefore be understood that the ratio between thenumber of m₁-bit channel words and the number of m₂-bit channel wordscan be determined in dependence upon a chosen measure of DC-control.

[0032] Another method according to the invention is characterized inthat the coding state is further being established in dependence uponthe n-bit information word, thereby allowing to distinguish this n-bitinformation word by detecting the coding state.

[0033] In order to increase the rate of the information signal, it isadvantageous that the coding state is also dependent on the n-bitinformation word to be encoded. As a result, the same channel word canbe used more than one time. In this way, the number of different channelwords necessary to construct a channel code is reduced, resulting in amore efficient code. Using states in the framework of a so-calledfinite-state-machine (FSM) for the characterization of the channel codesC₁ and C₂, therefore provides a possibility of establishing an overallcode with a high rate due to the multiple use of the same channel wordwith different next-states. At the decoder, it is the channel word incombination with the next-state, that uniquely determines thecorresponding information word.

[0034] Another method according to the invention is characterized inthat the coding states of channel code C₁ and the coding states ofchannel code C₂ are further arranged that a limited number of channelwords is substituted for other channel words or patterns, these otherchannel words or patterns not belonging to the sets of channel words ofchannel code C₁ and channel code C₂.

[0035] In a practical design of a channel code based on the combinationof two codes C₁ and C₂ according to the invention, there is some extraroom for the design of limited, stochastic control on top of theguaranteed control. Stochastic control is understood to be the kind ofcontrol in which the actual use of this control depends on the actualdata content (information words) that enters the encoder.

[0036] The existence of the room for stochastic DC-control is due to thefact that—in a practical code—some specific patterns do not occur in thechannel bitstream under normal application of the channel code; thesepatterns can then be used as substitution patterns for other patternsthat are allowed in the channel bitstream.

[0037] By substituting a limited number of channel words or patterns forother channel words or patterns not belonging to the channel words orpatterns present in the binary channel signal before the substitutions,additional DC-control can be accomplished, for instance, if thesubstitutions imply a parity inversion.

[0038] The coding methods as described in the above embodiments have thefollowing advantages, which are obvious or will be clarified in theFigure description, i) guaranteed DC-control, ii) reducederror-propagation because of the byte-oriented nature of the encoding,iii) simple single-pass encoding scheme, resulting in reduced encodercomplexity for performing encoding with look-ahead DC-control.

[0039] The invention also relates to a device for encoding. Theinvention also relates to a signal comprising a stream of databits of aconstrained binary channel signal. The invention further relates to arecord carrier and to a device for decoding.

[0040] These and other aspects of the invention will be furtherdescribed in the Figure description, in which

[0041]FIG. 1 shows an example of the coding method,

[0042]FIG. 2 shows an example of a 6-state Finite-State-Machine to beused for the main code (channel code C₁), aimed for the channelconstraints d=2, k=10,

[0043]FIG. 3 shows an example of a 6-state Finite-State-Machine to beused for the dual code (channel code C₂), aimed for the channelconstraints d=2, k=10,

[0044]FIG. 4 shows the code tables of the main code C₁,

[0045]FIG. 5 shows the code tables of the dual code C2,

[0046]FIG. 6 shows an example of how decoding of the next-state functionof the channel words of the main code is performed,

[0047]FIG. 7 shows an example of how decoding of the next-state functionof the channel words of the dual code is performed,

[0048]FIG. 8 shows a RDS-tree to be used for performing DC-control,

[0049]FIG. 9 shows the encoder path on a byte basis to be used forperforming DC-control for realizing efficient look-ahead encoding,

[0050]FIG. 10 shows a device for encoding according to the invention,

[0051]FIG. 11 shows a record carrier on which a signal comprising astream of databits of a constrained binary channel signal, obtainedafter carrying out a method according to the invention is recorded in atrack,

[0052]FIG. 12 shows an enlarged portion of the record carrier of FIG.11,

[0053]FIG. 13 shows a device for decoding according to the invention,

[0054]FIG. 14 shows a recording device according to the invention forrecording information,

[0055]FIG. 15 shows a reading device according to the invention forreading out a record carrier,

[0056]FIG. 16 shows a Finite-State Machine, full-bit description ford=1,

[0057]FIG. 17 shows a Finite-State Machine, half-bit description ford=1,

[0058]FIG. 18 shows a 2-state Finite-State Machine for d=1,

[0059]FIG. 19 shows a code alternation of channel code C₁ and channelcode C₂ for d=1,

[0060]FIG. 20 shows a 5-state Finite-State Machine, half-bit descriptionfor d=1,

[0061]FIG. 21 shows a 7-state Finite-State Machine, half-bit descriptionfor d=1.

[0062]FIG. 1 shows graphically an example of the coding method. Usingthis method predetermined properties of the binary channel signal can beinfluenced, for example for guaranteed DC-control via the alternation oftwo codes C₁ and C₂ via an alternation pattern that is also known at thedecoder.

[0063] We consider two channel codes, C₁ and C₂. Both codes are appliedon n-bit symbols. Channel code C₁ is a high-rate code with n-to-m₁mapping, channel code C₂ is a low-rate code with n-to-m₂ mapping. Inthis example, for d=2, k=10, C₁ has a 8-to-15 mapping, and C₂ has a8-to-17 mapping (n=8, m₁=15, m₂=17). Guaranteed DC-control, i.e.DC-control for every possible sequence of information words is achievedif the following conditions are satisfied: for each n-bit symbol,channel code C₂ has two channel words, one with even and one with oddparity in order to influence the RDS-value of the binary channel signal;for each n-bit symbol, the two possible channel representations of codeC₂ have the same next-state. The Finite-State-Machines (FSMs) of codesC₁ and C₂, indicating the states and state characterisations of thechannel codes C₁ and C₂, have the same number of states, and the FSM arebased on the same approximate eigenvector (according to Franazek'sdefinition, see § 5.3.1. of the book “Codes for mass data storagesystems”, K. A. Schouhamer Immink, November 1999, Shannon FoundationPublishers (ISBN-90-74249-23-X), which implies that channel words endingwith a given number of zeroes have a certain multiplicity, irrespectiveof the fact whether they are part of a channel word from the main codeC₁ or from the dual code C₂. The approximate eigenvector in this case ofd=2, k=10 which satisfies an approximate eigenvector inequality is thefollowing: V_((d=2,k=10))={2,3,4,4,4,4,3,3,3,2,1}.

[0064] However, the characterization of the states of FSM₁ for C₁ andFSM₂ for C₂ may be different. These state characterizations are chosenin order to realize the constraints imposed on the binary channelsignal. These constraints can be, for example, runlength-limitingconstraints (d,k) or an RMTR constraint. In this way, the constraintsimposed on the binary channel signal, formed by concatenating the m₁-bitchannel words and the m₂-bit channel words, are satisfied. We can callchannel code C₁ the main code, whereas channel code C₂ is referred to asthe dual code. The upper part of FIG. 1 depicts an n-bit informationword 1 which is converted into an m₁-bit channel word 2 via a channel C₁or into an m₂-bit channel word 3 via a channel code C₂.

[0065] The two available m₂-bit channel words are indicated in FIG. 1 bythe corresponding parities, “0” and “1”. The arrows in the lower part ofthis Figure depict the “flow” through the coding states of theFinite-State-Machines FSM₁ and FSM₂ when converting the informationwords. It can be seen that when converting an information word into anm₁-bit channel word, only one arrow points from the coding state of thechannel word to the coding state of the next channel word, whereas whenconverting an information word into an m₂-bit channel word, two arrowspoint from the coding state of the channel word to the coding state ofthe next channel word, indicating the choice between the two availablem₂-bit channel words.

[0066] The lower part of FIG. 1 depicts that for each information word(256 entries as the information words are 8 bits long, n=8) two m₂-bitchannel words are available with opposite parities and with the samenext-state. When converting an n-bit information word into an m₂-bitchannel word, this m₂-bit channel word can be chosen from the twoavailable m₂-bit channel words. In this example, this choice in used tocreate a DC-balanced or DC-free channel code.

[0067]FIG. 2 shows an example of the state characterization for a6-state Finite-State-Machine to be used for the main code (channel codeC₁). In this example the channel constraints to be complied with are d=2and k=10 and the channel code C₁ has a 8-15 mapping. FIG. 3 shows anexample of a 6-state Finite-State-Machine to be used for the dual code(channel code C₂). In this example the channel constraints to becomplied with are d=2 and k=10 and the channel code C₂ has a 8-17mapping.

[0068] In these Figures, a notation of “−10²|”, as can be found in thecolumn words IN in state 1 of the main code, indicates all channel wordswith an ending “100”. In the same way “|010¹⁰1−”, as can be found in thecolumn words OUT of state 2 of the main code, indicates all channelwords with a beginning “0100000000001”.

[0069] The Finite-State-Machines (FSMs) of codes C₁ and C₂have the samenumber of states, and the FSMs are based on the same approximateeigenvector, which implies that channel words ending with a given numberof zeroes have a certain multiplicity, irrespective of the fact whetherthey are part of a channel word from the main code C₁ or from the dualcode C₂. In the FSM of the dual code C₂, each branch leaving a statecorresponds to two possible channel words (word-pair) with i) oppositeparity and ii) the same next-state. The FIGS. 2 and 3 show that themultiplicity of any channel word in the 6-state FSMs ranges between 1and 4.

[0070] A lot of channel words or word-pairs are used more than onceacross different states. By appropriate mating, i.e. grouping of thesame combination of channel words or word-pairs together withnext-states to one single table entry for more than one state, errorpropagation can be reduced because a precise distinction of the statesleading to the given channel word has become irrelevant for thesechannel words or word pairs. In fact, the codes C₁ and C₂ allow fullstate-independent decoding.

[0071] The skilled person is familiar with channel codes comprisingdifferent states, the states forming a Finite-State-Machine. Detailedinformation on state-coding can be found in literature, for example inEuropean Patent Specification EP 0 745 254 B1 (PHN 14.746) or in thebook “Codes for mass data storage systems”, K. A. Schouhamer Immink,November 1999, Shannon Foundation Publishers (ISBN-90-74249-23-X).

[0072] In § 5.3 of this book it is explained that, in order to be ableto construct a sequence of channel words complying with the constraintsimposed on a channel code, at least M words that terminate at the sameor other principal states must emanate from each -coding state. Theexistence of a set of coding states is therefore a necessary conditionfor the existence of a code for the specified number of informationwords (256 in case of an 8-bit information word). It can be shown thatif an approximate eigenvector satisfies an approximate eigenvectorinequality, then a fixed-length code with the predetermined constraintsand other parameters of the code can be ascertained. More details can befound in § 5.3.1 of this book and in the literature references therein.

[0073] The invention in the above embodiment is not limited to a methodof encoding in order to realize a binary channel signal with guaranteedDC-control and reduced error-propagation, with the parameters d=2, k=10,n=8, m₁=15, m₂=17; a skilled person can apply the teaching of the methodof encoding according to the invention, without departing from the scopeof the invention, to generate a binary channel signal with, for example,d=2, n=7 or d=2 or n=13. He can, for example, also generate a binarychannel signal with a d=1 constraint.

[0074] For d=2 channel coding, the dual code C₂ of the combi-code needstwo channel bits extra for each channel word, in comparison with thechannel words of the main code (8-to-17 and 8-to-15 mappings of main anddual code, respectively). As a rule of thumb, the extra overhead interms of channel bits, needed for the design of the dual code is theinverse value of the rate R of the channel code. For d=2, k=10 themaxentropic capacity (theoretical upper limit for the rate) equals0.5418, thus around 1.846 “bits” are needed, which is rounded towards 2.

[0075] For d=1 channel coding, the situation is quite different. Themaxentropic capacity (without k-constraint) equals 0.6942, so thatusually codes are designed with a rate equal to ⅔. Byte-oriented codeswith an 8-to-12 mapping can then be used for the main code. The extranumber of “bits” needed for the channel words of the dual code nowamounts to 1.441 “bits”. Rounding towards 2 would lead to a dual codewith an 8-to-14 mapping, but then a rate-loss of more than a half bitresults, which makes the combi-code approach as such less interestingfrom the point of view of capacity. An extra measure, which will bediscussed in the following, is needed in order to avoid the aboverate-loss.

[0076] The present solution is worked out for the case d=1: for otherd-constraints, similar solutions can be devised. The solution for d=1 isto describe the channel coding in terms of half-bits, instead of thecommon description in terms of full bits. The standard full-bit FSM ford=1, and the half-bit FSM are shown in FIGS. 16 and 17, respectively.

[0077] In the half-bit FSM, one can make a distinction between EvenStates, where words entering these states have an even number oftrailing zeroes, and Odd States, where words entering these states havean odd number of trailing zeroes. The Even States are numbered {1,3,5},the Odd States are numbered {2,4}. In the half-bit FSM, we consider an8-to-24 mapping for the main code, and an 8-to-27 mapping for the dualcode. There exist now two versions of the main code: one with E-to-Ecoding, going from one of the states {1,3,5} towards one of the states{1,3,5}, the other with O-to-O coding, going from one of the states{2,4} towards one of the states {2,4}. There also exist two versions ofthe dual code: one with E-to-O coding, going from one of the states{1,3,5} towards one of the states {2,4}, the other with O-to-E coding,going from one of the states {2,4} towards one of the states {1,3,5}. Itis convenient to consider a two-state FSM for the encoding with thecombi-code, consisting of the E and the 0 state, as shown in FIG. 18.Encoding with the main code does not lead to a state change (E→E orO→O), whereas encoding with the dual code always leads to a state change(E→O or O→E) because the number of half-bits in a channel word of thedual code is odd.

[0078] The encoding sequence for successive segments of the combi-codeis shown in FIG. 19. A segment is a sequence of source words (bytes),the first of which is to be encoded with the dual code C₂, and allsubsequent source words (bytes) are to be encoded with the main code C₁.

[0079] For the generation of channel words for the two main codes, weadopt the following argumentation. A full-bit channel word (of length 12bits) can be converted into a half-bit channel word (of length 24half-bits) for the E-state via the conversion rules 0→00 and 1→01,implying that a full-bit channel word |0^(n)1→^(m)| is converted into|0^(2n+1)1→10^(2m)|. The arrow from “1” to “1” indicates any validsequence according to the respective FSMs. Note that due to theconversion, there can only be an odd number of zeroes in between twoones of the half-bit word, in agreement with the half-bit FSM.

[0080] A full-bit channel word can be converted into a half-bit channelword for the O-state via the conversion rules 0→00 and 1→10, implyingthat a full-bit channel word |0^(n)1→10^(m)| is converted into|0^(2n)1→10^(2m+1)|.

[0081] The generation of words for the dual codes is slightly moreinvolved. For the E-state, we convert a 13-bit channel word|0^(n)1→10^(m)| first into a half-bit channel word of length 26, andsupply an extra bit x at the end: |0^(2n+1)1→10^(2m)|. It is obviousthat for the E-state, only x=0 is allowed. The concatenation with theextra bit x=0 implies the construction of a half-bit channel word oflength 27, with the next-states being converted from {1} to {2}, andfrom {3,5} to {4}. For the 0-state, a similar procedure leads to the27-half-bit channel word |0^(2n)1→10^(2m+1)|x, where x=1 is allowed onlyif m >1, then leading to state 1 as next-state. The other possibilityx=0 is always allowed, leading to state 3 as next-state if m is even,and to state 5 as next-state if m is odd.

[0082] The possibility of constructing such a code is easily enumerated.We consider the approximate eigenvector {2,2,3,4,3} for the states ofthe half-bit FSM. Further, we restrict n≦5 and m≦5 (in view of ak-constraint, which is not imposed via the FSM). It is not our presentaim to construct a most optimal code (in terms of the k-constraint,given d=1), but we merely want to show the feasibility of the proposedmeasures for the design of combicodes for d=1. For the main code, instate E with states {1,3,5}, i.e. code C₁ ^(E), we have for wordsleaving from state 1 that n≧1, and 519 words are available, which isenough since the state multiplicity of state 1 equals 2, thus 512 wordsare needed; for words leaving from states 3 and 5, we have that n≧0, and872 words are available, which is enough since the state multiplicity ofstates 3 and 5 equals 3, thus 768 words are needed.

[0083] For the main code, in state 0 with states {2,4}, i.e. code C₁^(O), we have for words leaving from state 2 that n≧1, and 638 words areavailable, which is enough since the state multiplicity of state 2equals 2, thus 512 words are needed; for state 4, we have that n≧0, and1072 words are available, which is enough since the state multiplicityof state 4 equals 4, thus 1024 words are needed.

[0084] For the dual code, we have to account for the “same next-state”property according to the present invention. For the dual code, in stateE with states {1,3,5}, i.e. code C₂ ^(E), we have for words leaving fromstate 1 that n≧1, and there are 132 even-parity and 130 odd-paritychannel words with state 2 as the next-state, and there are 384even-parity and 388 odd-parity channel words with state 4 as thenext-state, yielding a total of 514 possible entries for the dual code,which is enough since the state multiplicity of state 1 equals 2,requiring 512 entries; for words leaving from states 3 and 5, we havethat n≧0, and there are 220 even-parity and 220 odd-parity channel wordswith state 2 as the next-state, and there are 648 even-parity and 648odd-parity channel words with state 4 as the next-state, yielding atotal of 868 possible entries for the dual code, which is enough sincethe state multiplicity of states 3 and 5 equals 3, requiring 768entries.

[0085] For the dual code, in state 0 with states {2,4}, i.e. code C₂^(O), we have for words leaving from state 2 that n≧1, and there are 194even-parity an d 192 odd-parity channel words with state 1 as thenext-state, and there are 300 even-parity and 300 odd-parity channelwords with state 3 as the next-state, and there are 186 even-parity and186 odd-parity channel words with state 5 as the next-state, yielding atotal of 678 possible entries for the dual code, which is enough sincethe state multiplicity of state 2 equals 2, requiring 512 entries; forwords leaving from state 4, we have that n≧0, and there are 324even-parity and 324 odd-parity channel words with state 1 as thenext-state, and there are 504 even-parity and 504 odd-parity channelwords with state 3 as the next-state, and there are 312 even-parity and312 odd-parity channel words with state 5 as the next-state, yielding atotal of 1140 possible entries for the dual code, which is enough sincethe state multiplicity of state 4 equals 4, requiring 1024 entries.

[0086] In the case of d=1, k=7, the following eigenvector satisfies anapproximate eigenvector inequality:V_((d=1,k=7,s=2))={3,4,5,6,5,6,4,6,3,3,3,3,3,3,2,2}. The accompanyingFinite-State Machines, a 5-state and a 7-state Finite-State Machine,half-bit description for d=1, are shown in FIG. 20 and FIG. 21. In thecolumns Fan-Out Main Code and Fan-Out Dual Code of these Figures thenumber channel words is indicated. It can be seen that the number ofredundant words can be different for the main code or the dual code.

[0087]FIG. 4 shows the code tables of the main code (channel code C₁),d=2, k=10, RMTR=6, with the entry index representing the index of the8-bit information symbol (0-255). For each entry, one 15-bit longchannel word is listed together with the corresponding next-state.

[0088]FIG. 5 shows the code tables of the dual code C₂ (channel codeC₁), d=2, k=10, RMTR=6, with the entry index representing the index ofthe 8-bit information symbol (0-255). For each entry, the two 17-bitlong channel words (word-pairs) are listed together with thecorresponding next-states. These next-states are identical.

[0089] The systematic structure of the main code C₁ and the dual code C₂realized a guaranteed control of the extra desired properties of thechannel bitstream (like a DC-free property). In an embodiment of achannel code based on the combination of two codes C₁ and C₂, there issome extra room for the design of (limited) stochastic control on top ofthe guaranteed control. Stochastic control is understood to be ofcontrol in which the actual use of this control depends on the actualdata content that enters the encoder.

[0090] The existence of the room for stochastic DC-control is due to thefact that—in a practical code—some specific patterns do not occur in thechannel bitstream under normal application of the channel code; thesepatterns can then be used as substitution patterns for other patternsthat are allowed in the channel bitstream. For instance, if thesubstitutions imply a parity inversion, then the substitutions can beused for additional DC-control, in the same sense as the substitutiontable is used in the EFM-Plus code. The evaluation which pattern is tobe selected can be performed on the basis of an RDS-related criterion,e.g. with one byte look-ahead. Although the invention as described sofar is related to a channel code with a guaranteed control in thecombination of two codes, the invention also relates to using thisstochastic control in a limited number of substitutions.

[0091] We will outline below some of the possibilities (referred to as Ato O) of stochastic control for the main code C₁ and dual code C₂according to the code tables of FIGS. 4 and 5. We limit ourselves hereto those which are the easiest to be implemented. For both the main anddual code we have the possible substitutions (where bits betweenbrackets, like (zu) refer to 17-bit channel words of channel code C₂):

[0092] A.

[0093] |100 100 000 100 0 xy (zu)→|100 100 00 100 0 xy (zu) , if theRMTR=6 constant is not violated.

[0094] B.

[0095] |010 010 000 010 00x (yz)→|010 010 010 010 00x (yz) , if theRMTR=6 constraint is not violated, and when the current state is notstate 3.

[0096] C.

[0097] |001 001 000 001 000 (xy)→|001 001 001 001 000 (xy) , if theRMTR=6 constraint is not violated and when the current state is notstate 3.

[0098] D.

[0099] If a channel word has as an ending: −10², the followingsubstitutions can be applied on the next channel word:

[0100] 10⁵1−→0⁶1−

[0101] 10⁶1−→0⁷1−

[0102] 10⁷1−→0⁸1−

[0103] E.

[0104] If a channel word has as an ending: −10³, the followingsubstitutions can be applied on the next channel word:

[0105] 10⁵1−→0⁶1−

[0106] 10⁶1−→0⁷1−

[0107] F.

[0108] If a channel word has as an ending: −10⁴, the followingsubstitutions can be applied on the next channel word:

[0109] 10₅1−→0⁶1−

[0110] G.

[0111] If a channel word has as an ending: −10⁶, the followingsubstitutions can be applied on the next channel word:

[0112] 10²1−→0³1−

[0113] 10³1−→0⁴1−

[0114] H.

[0115] If a channel word has as an ending: −10⁷, the followingsubstitutions can be applied on the next channel word:

[0116] 10²1−→0³1−

[0117] I.

[0118] If a channel word has as an ending: −10⁹, the followingsubstitutions can be applied on the next channel word:

[0119] 010⁵1−→010²10²1−, if the RMTR=6 constraint is not violated.

[0120] J.

[0121] If a channel word has as an ending: −10¹⁰, the followingsubstitutions can be applied on the next channel word:

[0122] 10²10²1−→10⁵1−

[0123] 10²10³1−→10⁶1−

[0124] 10²10⁴1−→10⁷1−

[0125] 10²10⁷1−→10¹⁰1−

[0126] For the main code C₁ only, we have as extra substitutions:

[0127] K.

[0128] |10²10⁵10⁴x|→|10⁸10⁴x|

[0129] L.

[0130] |10²10⁶10²xy|→|10⁹10²xy|

[0131] M.

[0132] If a channel word has as an ending: −10^(n), the followingsubstitutions can be applied on the next channel word:

[0133] 0²10²10⁷10|→|0²10¹⁰10|For 2≦n≦8.

[0134] N.

[0135] 0⁵10²10⁵x|→|0⁵10⁸x|

[0136] O.

[0137] |0⁹10²10²|→0⁹10⁵|

[0138] It must be stressed that whenever a possible substitution (underA up to O) violates the run length constraints (k=10, RMTR=6), thesubstitution is not performed.

[0139] In FIG. 6 is shown of how the next-state can be decoded for thechannel words of the main code. In FIG. 7 is shown how the next-statecan be decoded for the channel words of the dual code.

[0140] When decoding a channel word, either from the main code C₁ orfrom the dual code C₂, into an 8-bit information word, no knowledge ofthe current state is needed. Therefore, this decoding is calledstate-independent decoding. On the other hand, knowledge of thenext-state is needed in order to be able to uniquely decode the channelwords in the case of multiple occurrence of the given channel word. Infact, a code word is uniquely represented not only by the given channelword, but by the combination of channel word and next-state.

[0141] In FIGS. 6 and 7 it can be seen that, for determination of thenext-state, a decoding window with a decoder look-ahead of a maximum of12 bits and 14 bits into the next channel word must be performed, incase the next channel word is encoded with the main or dual coderespectively. The entries in the tables of FIGS. 6 and 7 where thismaximum decoder look-ahead is necessary are indicated with arrows. Thisdecoder look-ahead must not be confused with the look-ahead encoding forimproved DC-control. The asterisks in the FIGS. 6 and 7 indicate thatall possible bit-combinations are allowed, as long as the imposedconstraints are met.

[0142] When decoding the channel words into the information words, aso-called hashing-technique can be used, as will be explained below.Using this technique results in a reduced hardware complexity, i.e. asmaller number of gates, necessary to implement the decoder algorithm.We will describe one particular implementation in more detail. Decodingthe channel words of the main code, using the hashing technique isperformed as follows. Via enumerative decoding for d=2 the 15-bitchannel word is converted into a 9-bit word by 15-to-9 mapping.Enumerative decoding is decoding in which the channel words to bedecoded are computed by an algorithmic procedure based on the d=2constraint instead of storing all the channel words in a table (for moreinformation about enumerative coding refer to chapter 6 of the book“Codes for mass data storage systems”, K. A. Schouhamer Immink, November1999, Shannon Foundation Publishers, ISBN-90-74249-23-X). The number ofthe next-state is decoded via 2-bit coding in 2 bits because the maximummultiplicity of channel words equals 4. The 9-bit word and the 2-bitstate word results in an 11-bit index. This 11-bit index is convertedinto the 8-bit information word with a hashing table for the main code,this hashing table comprising a table with at maximum 2048 entries(=2¹¹) (state-independent decoding).

[0143] When decoding the channel words of the dual code, the hashingtechnique is performed as follows. Via enumerative decoding for d=2 the17-bit channel word is converted into a 10-bit word by 17-to-10 mapping.The number of the next-state is decoded via 2-bit coding in 2 bits. The10-bit word and the 2-bit state word results in a 12-bit index. This12-bit index is converted into the 8-bit information word with a hashingtable for the dual code, this hashing table comprising one single tablefor all 6 states and both parities and 4096 entries (=2¹²).

[0144] In FIG. 8 an RDS-tree to be used for performing DC-control isshown. RDS stands for the Running Digital Sum, which is a measure of theDC-content of the binary channel signal. As said before, for each m₂-bitchannel word to be encoded, DC-control can be performed. In order torealize the most effective DC-control, it is advisable to “lookahead” inorder to determine which choice of m₂-bit channel word, out of the twoavailable m₂-bit channel words, results in the best RDS-value. As can beseen in FIG. 8, in order to be able to look-ahead N decisions, 2^(N)possible paths of the RDS-tree must be calculated. For N=3, 8 possiblepaths must be calculated. It is clear that the number of paths to becalculated is only depending on the number of m₂-bit channel words to beencoded; the number of m₁-bit channel words is not important as noadditional paths are added when encoding an m₁-bit channel word.

[0145]FIG. 8 shows the decision tree with depth N, as it applies ingeneral, i.e. both to the encoding along the distinct paths and to theevaluation criterion. FIG. 9 shows the encoding tree with largelyreduced complexity, which becomes possible due to the “samenext-state”property of the dual code C₂. Although the RDS-criterion needs still tobe evaluated along the distinct paths, the encoding of bytes with C₁needs to be done only a single time, whereas bytes to be encoded withC₂, need, of course, to be encoded twice.

[0146] Consider a block of N*n_(B) bytes, comprising N bytes related toa channel word of the dual code and comprising N*(n_(B)−1) bytes relatedto channel words of the main code. It can be calculated that, in thecase of the RDS-tree of FIG. 8, the number of bytes to be encoded inorder to perform look-ahead DC-control is (2^(N)*n_(B)) bytes; It cansimilarly be calculated that, in the case of FIG. 9, the number of bytesto be encoded in order to perform look-ahead DC-control is N*(n_(B)+1)bytes.

[0147] In conclusion, it is shown that, in order to realize efficientlook ahead encoding for DC-control, the coding method according to theinvention is arranged so that for each n-bit symbol, the two possiblechannel representations of code C₂ have the same next-state.

[0148]FIG. 10 shows a device for encoding according to the invention. Inthis encoding device 100, a stream of databits of a binary informationsignal 101 is converted into a stream of databits of a constrainedbinary channel signal 103. The encoding device 100 comprises a converter102 for converting the n-bit information words into m₁-bit channel wordsand for converting the n-bit information words into m₂-bit channelwords, in accordance with the coding method, for example in accordancewith the code table of the main code C₁ and the dual code C₂ as shown inFIGS. 4 and 5. The encoding device 100 further comprisesstate-establishing means 104 for establishing a coding state of them₁-bit channel words and of the m₂-bit channel words. Using this codingstate, the converter 102 can convert the next n-bit information word.

[0149]FIG. 11 shows, by way of example, a record carrier 110 on which asignal comprising a stream of databits of a constrained binary channelsignal, obtained after carrying out a method according to the inventionis recorded in a track. FIG. 12 shows an -enlarged portion of the recordcarrier of FIG. 11.

[0150] The record carrier shown is of an optically detectable type. Therecord carrier may also be of a different type, for example, amagnetically readable type. The record carrier comprises informationpatterns arranged in tracks 111. FIG. 12 shows an enlarged portion 112of one of the tracks 111. The information pattern in the track portion112 shown in FIG. 12 comprises first sections 113, for example, in theform of optically detectable marks and second sections 114, for example,intermediate areas lying between the marks. The first and secondsections alternate in a direction of the track 115. The first sections113 present first detectable properties and the second sections 114present second properties which are distinguishable from the firstdetectable properties, The first sections 113 represent bit cells 116 ofthe modulated binary signal S having one signal level, for example thelow signal level L. The second sections 114 represent bit cells 117having the other signal level, for example the high signal level H. Therecord carrier 110 may be obtained by first generating the modulatedbinary channel signal and then providing the record carrier with theinformation pattern. If the record carrier is an optically detectabletype, the record carrier can then be obtained by means of mastering andreplica techniques known to a person skilled in the art.

[0151]FIG. 13 shows a device for decoding. In this decoding device 132,a stream of databits of a constrained binary channel signal 131 isconverted into a stream of databits of a binary information signal 134.The decoding device 132 comprises a converter for converting theconstrained binary channel signal 131 into the stream of databits of abinary information signal. Decoding can be accomplished, for example, byusing a hashing technique as described in and with reference to FIGS. 6and 7. When decoding the binary channel signal 131, information aboutthe next channel word to be decoded is needed, as is explained in andwith reference to FIGS. 6 and 7. This information 133 is supplied to thedecoding device 132 before decoding the present channel word.

[0152]FIG. 14 shows a recording device for recording information. TheFigure shows a recording device for recording information, in which thedevice for encoding according to the invention is used, for example thedevice for encoding 100 shown in FIG. 10. The signal line 141 suppliesthe information words to be encoded to the device for encoding 100. Inthe recording device the signal line 142 for supplying the modulatedbinary channel signal is connected to a control circuit 143 for a writehead 144 along which a record carrier 145 of a writable type is moved.The write head 144 is of a customary type which is capable ofintroducing marks having detectable changes on the record carrier 145.The control circuit 143 may also be of a customary type generating acontrol signal for the write head in response to the modulated signalapplied to the control circuit 143, so that the write head 144introduces a pattern of marks that corresponds to the modulated signal.

[0153]FIG. 15 shows a reading device for reading out a record carrier.This Figure shows a reading device in which a device for decodingaccording to the invention is used, for example, the decoding device 132shown in FIG. 13. The reading device comprises a read head 152 of acustomary type for reading out a record carrier 151 according to theinvention which record carrier 151 carries an information pattern thatcorresponds to the modulated binary channel signal according to theinvention. The read head 152 then produces an analog read signalmodulated in accordance with the information pattern read out by theread head 152. Detection circuit 153 converts this read signal incustomary fashion into a binary signal, which is applied to the decodingcircuit 132.

[0154] Whilst the invention has been described with reference topreferred embodiments therefor, it is to be understood that these arenot limitative examples. Thus, various modifications may become apparentto those skilled in the art, without departing from the scope of theinvention, as defined by the claims.

[0155] For example, instead of using one main code and one dual code, itis also possible to create a stream of channel words, without departingfrom the scope of the invention, by using a combination of more than onemain code and/or more than one dual code. By appropriately mixing thesecodes, the constraints of the stream of channel words can still becomplied with.

[0156] For example, the scope of the invention is not limited to amethod of encoding an information word into one m₁-bit channel wordfollowed by one m₂-bit channel word. The number of information words tobe encoded into m₁-bit channel words before encoding an information wordinto a m₂-bit channel word is not prescribed.

[0157] For example, the scope of the invention is not limited to abinary code. Without deviating from the gist of the invention, theinvention can be applied to multi-level codes, ternary codes or otherM-ary codes. The number of different m₂-bit channel words for each n-bitinformation word must at least be two and in an advantageous situation,this number is equal to the number of values of the multivalued“parity”-parameter, while the “parities” of the channel words must atleast cover all the different values at least once. In the case of aternary code (with values −1, 0 and 1) this implies that at least threedifferent m₂-bit channel words with “parities” −1, 0 and 1 are presentin the channel code C₂ (with the same next-state).

[0158] Furthermore, the invention resides in each and every novelcharacteristic feature or each and every combination of characteristicfeatures.

1. A method of converting a stream of databits of a binary informationsignal into a stream of databits of a constrained binary channel signal,wherein the stream of databits of the binary information signal isdivided into n-bit information words, said information words beingconverted into m₁-bit channel words in accordance with a channel codeC₁, or m₂-bit channel words, in accordance with a channel code C₂, wherem₁, m₂ and n are integers for which it holds that m₂>m₁≧n, wherein them₂-bit channel word is chosen from at least two m₂-bit channel words, atleast two of which have opposite parities, the concatenated m₁-bitchannel words and the m₂-bit channel words complying with a runlengthconstraint of the binary channel signal, characterized in that themethod comprises the repetitive and/or alternate steps of: selecting them₁-bit channel word from a set out of a plurality of sets of m₁-bitchannel words, each set comprising only m₁-bit channel words having abeginning part out of a subset of beginning parts of the m₁-bit channelwords, each set being associated with a coding state of channel code C₁,the coding state being established in dependence upon an end part of thepreceding channel word, or: selecting the m₂-bit channel word from a setout of a plurality of sets of m₂-bit channel words, each set comprisingonly m₂-bit channel words having a beginning part out of a subset ofbeginning parts of the m₂-bit channel words belonging to said set, eachset being associated with a coding state of channel code C₂, the codingstate being established in dependence upon an end part of the precedingchannel word, the end parts of the m₁-bit channel words in a codingstate of channel code C₁ and the beginning parts of the m₂-bit channelwords in a set of channel code C₂ being arranged to comply with saidrunlength constraint.
 2. A method according to claim 1 , characterizedin that the number of coding states of channel code C₁ is equal to thenumber of coding states of channel code C₂.
 3. A method according toclaim 1 or 2 , characterized in that the end part of any m₁-bit channelword has a multiplicity y₁, the multiplicity y₁ being the number ofdifferent states of the channel code C₁ said end part may establish, andthat the end part of any m₂-bit channel word has a multiplicity y₂, themultiplicity y₂ being the number of states of the channel code C₂ saidend part may establish and in that y₁=y₂ if the end part of the m₁-bitchannel word is equal to the end part of the m₂-bit channel word.
 4. Amethod according to claim 1 , 2 or 3, characterized in that said atleast two m₂-bit channel words establish the same state.
 5. A methodaccording to claim 1 , characterized in that the sets of channel wordsof channel code C₁ and the sets of channel words of channel code C₂ arearranged that binary channel signal formed by the concatenated m₁-bitchannel words and the m₂-bit channel words comply with a d=2 constraintand a k=10 constraint.
 6. A method according to claim 1 or 5 ,characterized in that the sets of channel words of channel code C₁ andthe coding states of channel code C₂ are arranged that binary channelsignal formed by the concatenated m₁-bit channel words and the m₂-bitchannel words comply with a Repeated-Minimum-Runlength-Limitation=6constraint on the binary channel.
 7. A method according to claim 1 ,characterized in that n=8, m₁=15, m₂=17.
 8. A method according to claim1 , 2 , 3 or 4, characterized in that the ratio between the number ofm₁-bit channel words and the number of m₂-bit channel words isdetermined in dependence of a chosen measure of DC-control.
 9. A methodaccording to claim 1 , characterized in that the coding state is furtherbeing established in dependence upon the n-bit information word, therebyallowing to distinguish this n-bit information word by detecting thecoding state.
 10. A method as claimed in claim 1 , 2 , 3 or 4,characterized in that the coding states of channel code C₁ and thecoding states of channel code C₂ are further arranged that a limitednumber of channel words is substituted for other channel words orpatterns, these other channel words or patterns not belonging to thesets of channel words of channel code C₁ and channel code C₂.
 11. Adevice for encoding a stream of databits of a binary information signalinto a stream of databits of a constrained binary channel signal, forperforming one of the methods as claimed, the device comprising ann-to-m₁-bit converter for converting the n-bit information words intom₁-bit channel words, an n-to-m₂-bit converter for converting the n-bitinformation words into m₂-bit channel words, state-establishing meansfor establishing a coding state of the m₁-bit channel words and of them₂-bit channel words, which n-to-m₁ bit converter is further arrangedfor selecting the m₁-bit channel word depending on the end part of thepreceding channel word, which n-to-m₂ bit converter is further arrangedfor selecting the m₂-bit channel word depending on the end part of thepreceding channel word.
 12. A device for encoding according to claim 11, characterized in that the device further comprises writing means forwriting an information pattern on a record carrier.
 13. A signalcomprising a stream of databits of a constrained binary channel signal,obtained after carrying out one of the methods as claimed.
 14. A recordcarrier on which the signal as claimed is recorded in a track, in whichinformation patterns represent the signal portions, which informationpatterns comprise first and second parts, alternating in the directionof the track, the first parts presenting detectable properties and thesecond parts presenting detectable properties which are distinguishablefrom the first properties, the parts having the first propertiesrepresenting bit cells having the first logic value and the parts havingthe second properties representing the bit cells having the second logicvalue.
 15. A device for decoding a stream of databits of a constrainedbinary channel signal into a stream of databits of a binary informationsignal, the device comprising converting means for converting the signalas claimed into a bit string of bits having a first or a second value,the signal containing the m₁-bit channel words and the m₂-bit channelwords, the bit string comprising the n-bit information words, theconverting means being arranged to convert the m₁-bit channel words andm₂-bit channel words into n-bit information words, wherein oneinformation word is assigned to one channel word to be converted.
 16. Adevice for decoding according to claim 15 , characterized in that thedevice further comprises reading means for reading out an informationpattern from a record carrier.